Methods for improving data rates and the performance of wireless communication systems using H-ARQ processes are being investigated in the Third Generation Partnership Project (3GPP).
An H-ARQ scheme is used to generate transmissions and retransmissions with low latency. H-ARQ is a variation of an automatic repeat request (ARQ) error control method, which provides better performance than an ordinary ARQ method at the cost of increased implementation complexity. H-ARQ can be used in stop-and-wait retransmission or in selective repeat retransmission. Stop-and-wait retransmission is simpler to use. However, waiting for a receiver's acknowledgment of a signal reduces efficiency. Thus, multiple stop-and-wait H-ARQ processes are used in parallel to overcome the positive acknowledgement (ACK)/negative acknowledgement (NACK) round-trip delay due to this mechanism. Further, multiple H-ARQ processes allow high priority traffic to be sent immediately using a new H-ARQ process, rather than being stalled behind packets in transmission using an existing H-ARQ process. For example, when one H-ARQ process is waiting for an ACK, another H-ARQ process can be used to send more data.
In 3GPP, protocol messaging configures H-ARQ behavior, including H-ARQ memory availability. More specifically, the prior art permits protocol messages to configure an H-ARQ process with a buffer size and to exchange the buffer size with a communicating peer device, such as a WTRU or a Node-B. In the prior art, each H-ARQ process is configured with a particular H-ARQ memory limit. This configuration presents two limitations and inefficiencies. First, certain radio bearers may benefit from more H-ARQ processes, each with small memory requirements. Second, an application may benefit from fewer H-ARQ processes with larger buffer limits when the application has large memory requirements but can tolerate an increased number of H-ARQ retransmissions because the application does not have stringent delay requirements.
A challenge in implementing the H-ARQ mechanism is the receive memory requirement to buffer soft decoding decisions in the H-ARQ memory needed to implement incremental redundancy schemes.
Two of the desired improvements of long term evolution (LTE) of wideband code division multiple access (WCDMA) for universal mobile telecommunication systems (UMTS) are higher data rates as well as improved handling of different applications, particularly with different quality of service (QoS) requirements. LTE is also referred to as evolved universal terrestrial radio access (E-UTRA). To provide these desired improvements, LTE working groups are discussing flexible frame and transmission time interval (TTI) formats. Additionally, particular delay insensitive applications are able to tolerate a greater number of retransmissions.
As data rates increase, the amount of H-ARQ memory, (i.e. soft memory), needed for H-ARQ processes becomes a considerable cost factor for a baseband chipset. Therefore, H-ARQ memory optimizations are potentially a considerable design benefit. Unfortunately, the current H-ARQ memory allocation mechanism is too restrictive to handle these considerations. As a result, a new mechanism that permits for a more dynamic and flexible H-ARQ memory configuration is necessary.